Tilera announced the new TILE-Gx100, which is the world’s first 100-core processor. The TILE-Gx100 is actually part of the company’s TILE-Gx family, other three processors in the family has 16, 36 and 64 cores.
The Tilera TILE-Gx is based on a nique architecture that scales well beyond the core count of traditional microprocessors. Tilera’s two-dimensional iMesh interconnect eliminates the need for an on-chip bus and its Dynamic Distributed Cache (DDC) system allows each cores’ local cache to be shared coherently across the entire chip. The TILE-Gx family also raises the bar for performance-per-watt to new levels with ten times better compute efficiency compared to Intel’s next generation Core i7 (aka Westmere/Nehalem) processor.
Tilera’s TILE-Gx, fabricated in TSMC’s 40 nanometer process, operates at up to 1.5 GHz with power consumption ranging from 10 to 55 watts. Some technology highlights:
- Next-generation 64-bit core: New three-issue 64-bit core with full virtual memory system. Each core includes 32KB L1 I-cache, 32KB L1 D-cache and 256KB L2 cache, with up to 26MB total L3 coherent cache across the device.
- Enhanced SIMD instruction extensions: Improved signal processing performance with a 4 MAC/cycle multiplier unit delivering up to 600 billion MACs per second, more than 12x the fastest commercial DSP.
- Integrated high-performance DDR3 memory controllers: Two or four 72-bit controllers running up to 2133 MHz speeds with ECC support. Up to 1TB total capacity and powerful memory striping modes for maximum utilization.
- Hardware acceleration engines: On-chip MiCA (Multistream iMesh Crypto Accelerator) system delivers up to 40Gbps encryption and 20Gbps full duplex compression processing, tightly coupled to the iMesh for extremely low latency and wire-speed small packet throughput. In addition, a high-performance true random number generator (RNG) and public key accelerator enable up to 50,000 RSA handshakes per second.
- Packet processing accelerator: mPIPE (multicore Programmable Intelligent Packet Engine) system provides wire-speed packet classification, load balancing and buffer management. This flexible, C-programmable engine delivers 80 Gbps and 120 million packets-per-second of throughput for packets with multiple layers of encapsulation.
The TILE-Gx36 processor will be sampling in Q4 of 2010 with the other processors rolling out in the following two quarters.
